1. Technical Field
The present invention relates generally to computer systems, and more specifically to a cache controller for use with input/output devices.
2. Background Art
Computer systems generally have several different storage layers defining a memory hierarchy. These layers typically include registers in a central processing unit, main system memory, and mass storage, such as disks. The performance of these different levels is quite different; the processor registers are much faster than system memory, which in turn is significantly faster than access to mass storage.
In order to improve system performance, a cache, consisting of a small, fast memory, is often used between the central processor and system memory. The cache takes advantage of the locality of reference phenomenon within computer programs to store data which is likely to be reused into the fast memory.
A similar bottleneck occurs between system memory and the much slower mass storage devices and other input/output devices which need to transfer data to and from the system memory. Any system design which makes data transfer between input/output devices, which term as used herein includes mass storage devices, more efficient will have a positive impact on overall system performance. However, traditional caching technology such as used between a central processor and system memory does not work well with input/output devices.
This is due, in large part, to differences in access patterns found with a single central processing unit and a plurality of input/output devices. A central processor is a single unit accessing memory, and makes a large number of relatively random accesses to different locations throughout system memory. Memory accesses by input/output devices have a different pattern of use. Each device usually accesses only a few memory locations, but different devices access different memory locations. In addition, the different devices access memory in unpredictable patterns.
Since some input/output devices access memory relatively infrequently, a cache hit would seldom occur for those devices. This is especially true when some input/output devices, such as disks, read or write a large number of consecutive memory locations. After such a transfer, a cache would tend to be filled with data transferred by that device. Providing a separate cache memory for each input/output device is not generally feasible.
If there are some portions of the main system memory which are accessible by both the input/output devices and the central processor, the central processor may have to access such memory through the input/output cache in order to avoid a cache coherency problem with a normal CPU cache This tends to interfere with use of an input/output cache by the input/output devices.
It would be desirable for an input/output interface device to enable a central processor and input/output devices to have common access to a shared area of main system memory. It would further be desirable for such an interface to provide a mechanism whereby a portion of the memory address space is assigned to devices attached to an input/output bus.